1. Field of the Invention
The present invention relates to the field of fabrication and testing of gate array integrated circuits. Specifically, the present invention relates to assessing the performance and/or yield of generically fabricated gate array wafers so as to enable the allocation of the generically fabricated gate array wafers to a suitable application specific custom design. The present invention includes a method for providing fast turn high performance gate array or sea of gates integrated circuits. In particular, the present invention includes a high yield method for fabricating gate array integrated circuits having a much higher maximum speed performance specification than the semiconductor fabrication process used for the fabrication of the integrated circuits can generally guarantee.
2. Discussion of the Related Art
Gate array or sea of gates integrated circuits are well known in the art. It is to be understood that the term "gate array" as used hereinafter also includes sea of gates and sea of modules. An example of gate array technology is disclosed by R. Gregor et al. in a paper entitled "A One-million-circuit CMOS ASIC Logic Family" published in Proceedings of IEEE 1993 Custom Integrated Circuits Conference, pp. 23.1.1-23.1.4 (1993).
Such gate array integrated circuits are normally fabricated with an array of generic modules or transistors that can be interconnected via interconnection layers that are fabricated later and are customized to certain patterns relating to the customers' design. Wafers with the generic module arrays or transistor arrays are fabricated without the interconnection layers and are then inventoried for later customization after some simple generic parameter tests.
Performance testing typically includes measuring the speed of the silicon. The maximum operating frequency of the integrated circuit can be deduced from the speed of the silicon. Performance testing requires operating the integrated circuit through external connections which are typically applied to the integrated circuit's top metal layer.
Performance testing of the generic gate array wafers is not conventionally performed. In fact, prior to inventory, no performance testing is even possible because no metallization layers have been applied to the chip. Therefore, without a top metal layer to which to connect, the performance tester cannot make connection to the generic gate array wafer prior to inventory.
The speed performance of an integrated circuit depends on many factors. For example, the actual circuits implemented by the integrated circuit greatly affect the measured speed. The resistances, capacitances, and inductances created by wiring layer interconnections of active elements on the integrated circuit affect performance. The parasitic elements that are inevitably introduced during the semiconductor fabrication process used for the fabrication of the circuit affect performance. The parasitic elements are resistances, capacitances, and inductances. All wiring layers and the diffusion material used to form the transistors have finite non-zero resistances. Parasitic capacitances exist due to the proximity of neighboring devices and interconnection structures and due to the characteristic of the specific semiconductor fabrication process used. The capacitances and inductances of the interconnection of active elements depend on the lengths of the interconnecting elements, proximity to other interconnecting elements, and the capacitance and inductance per unit length, which are process dependent. The gain and characteristic of the active transistor elements are also process dependent.
The values of the parasitic elements, gains of active elements, and capacitance and inductance per unit length vary due to process variations from wafer to wafer in the same or different process lots and from die to die on the same wafer. The process parameters applied to each successive wafer can only be duplicated from wafer to wafer within a certain non-zero tolerance. Therefore, the processing of each wafer typically varies slightly within the tolerance which can be achieved with the process tools. This wafer-to-wafer process variation results in slightly different performance parameters for each wafer. Moreover, because all dies on the same wafer are physically positioned in different positions relative to the various components of the process tools, each of the dies on a given wafer is exposed to slightly different process conditions. However, the variation of the parameters between dies on the same wafer tends to be smaller than the variation of the parameters from wafer to wafer. In other words, the parameters tends to track from die to die on the same wafer.
The smaller inter-wafer and larger intra-wafer variations of these parameters cause a specific integrated circuit design to have upper and lower performance values. The upper and lower performance values represent the statistically best case and statistically worst case, respectively, that can reasonably be expected for the specific integrated circuit taking the above-mentioned process variations into account. In order to guarantee correct functionality of the circuit when it is used in a system, it is customary and necessary in engineering practice to use the lower performance value as the specification of the system including the integrated circuit. Therefore, the performance specification of the integrated circuit often sets the performance level of the system in which the integrated circuit exists.
If the worst case is used as the specification, then all parts will conform to the performance specification because all parts will, by definition, meet or exceed the worst case. Therefore, all dies which are correctly fabricated will be usable in a system. Therefore, this conventional specification strategy results in a somewhat low overall system performance level. The performance level is deemed to be somewhat low particularly because most of the integrated circuits can function successfully at significantly higher performance levels than that specified by the worst case.
One way to achieve higher system performance, and thereby solve the above-mentioned problem, is to sort the integrated circuit after it is completely fabricated through the semiconductor fabrication process. The dies are tested for functionality to separate the good dies from the bad dies. Bad dies are those dies which have fatal flaws in them such that they are inoperative and do not function correctly at any speed. The ratio of good dies to total dies is typically referred to as the "yield" of the process. The good dies are tested with special test vectors and procedures in order to separate the higher performance dies from the lower performance dies. The performance sorted dies can then be used in higher and lower performance systems accordingly depending on the requirements and the designs of the systems. This approach is suitable for systems where lower performance parts are acceptable for a lower performance version of the system.
FIG. 1 illustrates a typical design scenario. A nearly gaussian distribution of wafer speeds is assumed. The probability distribution 101 of a wafer having a maximum speed f is plotted having probability on the y-axis and speed on the x-axis. Three separate performance specifications are shown corresponding to three separate designs. Design A must have a speed of at least f1; design B must have a speed of at least f2; and design C must have a speed of at least f3. For the sake of convenience, the three performance specifications f1, f2, and f3 happen to divide the probability distribution 101 into thirds. The area 102 under the probability distribution 101 between f1 and f2 is 1/3; the area 103 under the probability distribution 101 between f2 and f3 is 1/3; and the area 104 under the probability distribution 101 between f3 and infinity is 1/3. In general, the performance specification and probability distributions may be arbitrary.
However, in many cases the higher performance parts are the only acceptable parts, thus the lower performance parts are disposed of as bad components and are categorized as bad dies. This approach increases the cost of the integrated circuit substantially due to the additional testing requirement and the lower yield due to the cost of the disposed lower performance parts.
FIG. 2 illustrates a conventional gate array fabrication method. At step 201, a conventional gate array integrated circuit manufacturer produces the gate array integrated circuit wafer stopping before the first interconnecting metal. The wafer is removed from the process tools and is inventoried at step 202 for all customers. At this point the wafer has no application specific fabrication associated with it; it is generic.
When a certain customer wishes to implement his application specific custom design, he retrieves the wafer from an inventory. At step 203, fabrication is resumed and the metallization layers are deposited and etched. This step 203 includes formation of the application specific custom metallization layers. At step 204 the wafer is cut into individual gate array integrated circuit dies. At step 205, performance testing on the individual gate array integrated circuit dies is performed. At step 206, the individual gate array integrated circuit dies are sorted according to their measured performance which was obtained in step 205.
Conventionally, since the integrated circuit is not yet complete at the time of inventory after generic fabrication, performances of the dies on the wafer are not fully characterized. It is not possible to do any performance testing at this time. Worst case parameters are assumed in order to guarantee functionality for all statistically possible variations of parameters.
FIG. 3 illustrates how the conventional method described in FIG. 2 applies to the hypothetical situation described in FIG. 1. The generic gate array integrated circuit wafers are fabricated at step 301 and inventoried at step 302. Some of the inventoried wafers are used at step 303 to fabricate the custom design A; others of the inventoried wafers are used at step 304 to fabricate the custom design B; while yet others of the inventoried wafers are used at step 305 to fabricate the custom design C. At step 306 it is determined that all design A parts meet the f1 performance specification. At step 307 it is determined that only two-thirds of the parts having design B meet the performance specification f2, and at step 309 one-third of the parts having design B are slower than f2. At step 308, it is determined that only one-third of the parts having design C meet the performance specification f3, and at step 310 it is apparent that two-thirds of the design C parts are slower than f3. Thus, in the high performance category, the acceptable yield is only approximately 33%.
As is apparent from the above discussion, a need exists for an integrated circuit fabrication method which increases the usable yield of gate array integrated circuits which must meet a high performance specification.